/* Generated automatically by the program `genattr-common'
   from the machine description file `md'.  */

#ifndef GCC_INSN_ATTR_COMMON_H
#define GCC_INSN_ATTR_COMMON_H

enum attr_type {TYPE_INTEGER, TYPE_TWO, TYPE_THREE, TYPE_ADD, TYPE_LOGICAL, TYPE_SHIFT, TYPE_INSERT, TYPE_MUL, TYPE_HALFMUL, TYPE_DIV, TYPE_EXTS, TYPE_CNTLZ, TYPE_POPCNT, TYPE_ISEL, TYPE_LOAD, TYPE_STORE, TYPE_FPLOAD, TYPE_FPSTORE, TYPE_VECLOAD, TYPE_VECSTORE, TYPE_CMP, TYPE_BRANCH, TYPE_JMPREG, TYPE_MFJMPR, TYPE_MTJMPR, TYPE_TRAP, TYPE_ISYNC, TYPE_SYNC, TYPE_LOAD_L, TYPE_STORE_C, TYPE_CR_LOGICAL, TYPE_MFCR, TYPE_MFCRF, TYPE_MTCR, TYPE_FPCOMPARE, TYPE_FP, TYPE_FPSIMPLE, TYPE_DMUL, TYPE_QMUL, TYPE_SDIV, TYPE_DDIV, TYPE_SSQRT, TYPE_DSQRT, TYPE_VECSIMPLE, TYPE_VECCOMPLEX, TYPE_VECDIV, TYPE_VECCMP, TYPE_VECCMPSIMPLE, TYPE_VECPERM, TYPE_VECFLOAT, TYPE_VECFDIV, TYPE_VECDOUBLE, TYPE_MFFGPR, TYPE_MFTGPR, TYPE_CRYPTO, TYPE_VECLOGICAL, TYPE_VECCMPFX, TYPE_VECEXTS, TYPE_VECMOVE, TYPE_HTM, TYPE_HTMSIMPLE, TYPE_DFP, TYPE_MMA};
enum attr_size {SIZE_8, SIZE_16, SIZE_32, SIZE_64, SIZE_128};
enum attr_dot {DOT_NO, DOT_YES};
enum attr_sign_extend {SIGN_EXTEND_NO, SIGN_EXTEND_YES};
enum attr_cr_logical_3op {CR_LOGICAL_3OP_NO, CR_LOGICAL_3OP_YES};
enum attr_indexed {INDEXED_NO, INDEXED_YES};
enum attr_update {UPDATE_NO, UPDATE_YES};
enum attr_maybe_var_shift {MAYBE_VAR_SHIFT_NO, MAYBE_VAR_SHIFT_YES};
enum attr_var_shift {VAR_SHIFT_NO, VAR_SHIFT_YES};
enum attr_cannot_copy {CANNOT_COPY_NO, CANNOT_COPY_YES};
enum attr_prefixed {PREFIXED_NO, PREFIXED_YES};
enum attr_cpu {CPU_PPC601, CPU_PPC603, CPU_PPC604, CPU_PPC604E, CPU_PPC620, CPU_PPC630, CPU_PPC750, CPU_PPC7400, CPU_PPC7450, CPU_PPC403, CPU_PPC405, CPU_PPC440, CPU_PPC476, CPU_PPC8540, CPU_PPC8548, CPU_PPCE300C2, CPU_PPCE300C3, CPU_PPCE500MC, CPU_PPCE500MC64, CPU_PPCE5500, CPU_PPCE6500, CPU_POWER4, CPU_POWER5, CPU_POWER6, CPU_POWER7, CPU_POWER8, CPU_POWER9, CPU_POWER10, CPU_RS64A, CPU_MPCCORE, CPU_CELL, CPU_PPCA2, CPU_TITAN};
enum attr_isa {ISA_ANY, ISA_P5, ISA_P6, ISA_P7, ISA_P7V, ISA_P8V, ISA_P9V, ISA_P9KF, ISA_P9TF, ISA_P10};
enum attr_cell_micro {CELL_MICRO_NOT, CELL_MICRO_CONDITIONAL, CELL_MICRO_ALWAYS};
#define INSN_SCHEDULING
#define DELAY_SLOTS 0

#endif /* GCC_INSN_ATTR_COMMON_H */
